CY62137FV30 MoBL®
2-Mbit (128K x 16) Static RAM
®
is ideal for providing More Battery Life™ (MoBL ) in portable
Features
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH or both BLE and
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
BHE are HIGH). The input and output pins (IO through IO ) are
placed in a high impedance state in the following conditions:
0
15
■ Wide voltage range: 2.20V–3.60V
■ Deselected (CE HIGH)
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
■ Outputs are disabled (OE HIGH
CY62137V, and CY62137EV30
■ Both Byte High Enable and Byte Low Enable are disabled
■ Ultra low standby power
(BHE, BLE HIGH)
❐ Typical standby current: 1 μA
❐ Maximum standby current: 5 μA (Industrial)
■ Ultra low active power
■ Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
from IO pins (IO through IO ) is written into the location
0
7
specified on the address pins (A through A ). If Byte High
0
16
Enable (BHE) is LOW, then data from IO pins (IO through IO
)
8
15
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
is written into the location specified on the address pins (A
0
through A ).
16
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
■ Available in Pb free 48-Ball VFBGA and 44-pin TSOP II
package
location specified by the address pins appear on IO to IO . If
0
7
Byte High Enable (BHE) is LOW, then data from memory
Functional Description
8
15
complete description of read and write modes.
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
For best practice recommendations, refer to the Cypress
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
128K x 16
RAM Array
IO0–IO7
IO8–IO15
BHE
WE
CE
COLUMN DECODER
CE
POWER DOWN
CIRCUIT
OE
BLE
BHE
BLE
Cypress Semiconductor Corporation
Document Number: 001-07141 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 2, 2008
CY62137FV30 MoBL®
DC Input Voltage
.......................................–0.3V to 3.9V
Maximum Ratings
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential ...........................................................-0.3V to 3.9V
Device
Range
V
CC
Temperature
CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Auto-E –40°C to +125°C
in High Z state
............................................-0.3V to 3.9V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Description
Test Conditions
Unit
[1]
[1]
Min Typ
2.0
Max
Min Typ
Max
V
V
V
V
I
Output HIGH Voltage
2.2 < V < 2.7
I
I
I
I
= –0.1 mA
= –1.0 mA
= 0.1 mA
= 2.1mA
2.0
2.4
V
V
OH
OL
IH
CC
OH
OH
OL
OL
2.7 < V < 3.6
2.4
CC
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
2.2 < V < 2.7
0.4
0.4
0.4
0.4
V
CC
2.7 < V < 3.6
V
CC
2.2 < V < 2.7
1.8
2.2
V
V
+ 0.3 1.8
+ 0.3 2.2
V
V
+ 0.3
V
CC
CC
CC
CC
CC
2.7 < V < 3.6
+ 0.3
V
CC
2.2 < V < 2.7
–0.3
–0.3
–1
0.6
0.8
–0.3
–0.3
–4
0.6
V
IL
CC
2.7 < V < 3.6
0.8
+4
+4
V
CC
Input Leakage Current GND < V < V
CC
+1
+1
μA
μA
IX
I
I
Output Leakage
Current
GND < V < V , Output disabled
–1
–4
OZ
O
CC
I
V
Operating Supply f = f
= 1/t
V
= V
CC(max)
= 0 mA
13
18
15
2
25
3
mA
CC
CC
max
RC
CC
Current
I
OUT
f = 1 MHz
1.6
2.5
CMOS levels
I
I
Automatic CE Power
Down Current – CMOS V > V – 0.2V, V < 0.2V
Inputs
CE > V – 0.2V,
1
5
1
20
μA
SB1
CC
IN
f = f
CC
IN
(address and data only),
max
f = 0 (OE, WE, BHE, and BLE), V = 3.60V
CC
[7]
Automatic CE Power
Down Current – CMOS
Inputs
CE > V – 0.2V,
1
5
1
20
μA
SB2
CC
V
> V – 0.2V or V < 0.2V,
CC IN
IN
f = 0, V = 3.60V
CC
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Input Capacitance T = 25°C, f = 1 MHz,
Max
Unit
C
10
10
pF
pF
IN
A
V
= V
CC
CC(typ)
C
Output Capacitance
OUT
Notes
4.
5.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
=V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
CC
CC
7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
/ I
specification. Other inputs can be left floating.
SB2 CCDR
Document Number: 001-07141 Rev. *F
Page 3 of 12
CY62137FV30 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
VFBGA
TSOP II
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
75
77
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
10
13
°C/W
JC
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveform
R1
ALL INPUT PULSES
90%
10%
V
CC
V
CC
90%
OUTPUT
10%
GND
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
2.5V (2.2V to 2.7V)
3.0V (2.7V to 3.6V)
Unit
Ω
R1
R2
16667
15385
8000
1.20
1103
1554
645
Ω
R
Ω
TH
TH
V
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
I
V
for Data Retention
1.5
V
DR
CC
Data Retention Current
V
V
= 1.5V, CE > V - 0.2V,
Ind’l/Auto-A
Auto-E
4
μA
CCDR
CC
CC
> V - 0.2V or V < 0.2V
IN
CC
IN
12
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
R
t
RC
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
V
V
CC(min)
CC(min)
V
> 1.5V
VCC
DR
t
t
R
CDR
CE or
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V ramp from V to V > 100 μs or stable at V > 100 μs.
CC(min)
CC
DR
CC(min)
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-07141 Rev. *F
Page 4 of 12
CY62137FV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
10
55
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
55
AA
Data Hold From Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
55
25
CE LOW to Data Valid
OE LOW to Data Valid
5
10
0
5
10
0
OE LOW to Low Z
18
18
20
20
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
45
45
55
55
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
PD
DBE
LZBE
HZBE
5
10
BLE/BHE LOW to Low Z
18
20
BLE/BHE HIGH to High Z
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
45
35
35
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
HA
0
0
SA
35
35
25
0
40
40
25
0
WE Pulse Width
PWE
BW
BLE/BHE LOW to Write End
Data Setup to Write End
SD
Data Hold From Write End
HD
18
20
WE LOW to High Z
HZWE
LZWE
10
10
WE HIGH to Low Z
Notes
11. Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
CC(typ)
OL OH
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals are ACTIVE to initiate a write and any of these
IL
IL
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-07141 Rev. *F
Page 5 of 12
CY62137FV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Figure 6. Read Cycle 2: OE Controlled
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
17. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .
IL
IL
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-07141 Rev. *F
Page 6 of 12
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